1. Field of the Invention
The invention relates to computer memory devices utilizing variable threshold MNOS transistors as memory elements and is particularly concerned with the decoder buffer circuit thereof.
2. Description of the Prior Art
U. S. Pat. No. 3,747,072, issued July 17, 1973 in the names of R. J. Lodi and H. A. R. Wegener, entitled "Integrated Static MNOS Memory Circuit" and issued to the present assignee, discloses a self-contained integrated memory utilizing variable threshold MNOS transistors as the memory elements. This memory arrangement operates in a variety of functional modes such as READ, WRITE and CLEAR in response to input control signals E and R/W with appropriate words of the memory being selected via address signals A.sub.1 and A.sub.2. Power is provided for the memory by supply potentials V.sub.G and V.sub.D.
Although the memory of said U.S. Pat. No. 3,747,072 provides satisfactory performance in the various operating modes, it was recognized that by utilizing a novel decoder buffer circuit improvements could be effected with respect to the required power supply potential, the power dissipation of the circuit and the read accesss time. In the device of said U.S. Pat. No. 3,747,072 the variable threshold transistors of the memory array 11 require application of -25 volts to their gate electrodes which -25 volts is provided on the word lines from the decoder buffers of the circuit. As described in said U.S. Pat. No. 3,747,072, the decoder buffer circuit associated with each word line is comprised of two serially connected transistors such as transistors 67 and 91. The transistor 67 operates in a source follower mode in its saturation region with the transistor 91 providing the load therefor. As described in the patent, -30 volts from the V.sub.D supply is provided on the line 85 and because of an approximate 5 volt drop across the source follower transistor 67, -25 volts is applied to the word line. The source follower transistor, such as 67, for the selected decoder buffer requires at least -30 volts on its gate electrode which potential is provided from the V.sub.D supply through the associated address decoder transistor such as transistor 41. In order for the transistor 41 to provide the -30 volt potential to the gate of the transistor 67, the potential V.sub.G applied to the gate of the transistor 41 must be at least -35 volts. For operational stability V.sub.G is chosen as -40 volts in the patent. Alternatively the V.sub.G and V.sub.D terminals may be tied together which would cause the transistor 41 to operate in its saturation region requiring a power supply potential of -35 volts for V.sub.D in order to provide -30 volts at the gate electrode of transistor 67. Thus it is appreciated that with both arrangements the power supply potential V.sub.D or V.sub.G must be two fixed threshold transistor voltage drops (V.sub.T) greater than the potential required at the word lines.
These extraneous voltage drops result in a power supply potential greater than that required to actually drive the memory transistors 15. A reduction of power supply potential from the required -35 volts to, for example, -30 volts would result in greater circuit yield since the higher the potential that is required to be applied to the circuit chip, the greater will be the propensity of the chip toward voltage breakdown.
As described in said U.S. Pat. No. 3,747,072, the decoder buffers operate as source followers in the WRITE mode. The source follower mode of operation requires a buffer decoder load transistor such as the transistor 91 in order that the word lines are discharged after the write operation. Thus in the WRITE mode current will flow through the serially connected transitors such as 67 and 91 when the write potential is applied from the buffer drive circuit resulting in unwanted power dissipation.
As described in said U.S. Pat. No. 3,747,072, the two serially connected decoder buffer transistors associated with each word line are utilized in both the READ mode and the WRITE mode and operate in both modes as a source follower. The read voltage is applied from the buffer drive circuit via the same circuit path used for writing. Since the fixed threshold transistors switch relatively slowly, approximately five times slower in the source follower mode than in the triode mode, the read access time of the memory is adversely affected. Since the same decoder buffer circuitry is utilized for both reading and writing, a compromise in design was necessitated to perform both operations with the same devices.
Additionally, the read and write potentials are applied via the buffer drive circuit by switching the power supply which technique may be less desirable than applying the read and write potentials to separate input pins as d.c. levels.